1. Field of the Invention
The present invention relates to a display apparatus such as a flat-panel display apparatus, a driving circuit for the display apparatus, and a semiconductor device for the driving circuit.
2. Description of the Related Art
The importance of an apparatus to mediate a man or woman and a machine (man-machine interface) has been increased with the advance of computer technology. Especially, a display apparatus as one of the man-machine interfaces on the output side is required to have higher performance. The display apparatus displays data outputted from a computer for a man to visibly recognize the data. Various kinds of display apparatuses are commercially available. A typical display apparatus is a flat-panel display and is widespread.
The flat-panel display apparatus is exemplified by a liquid crystal display and an organic electro-luminescence display apparatus using organic electro-luminescence. The organic electro-luminescence display apparatus has a merit that the display panel is thinner compared with the liquid crystal display. Moreover, the organic electro-luminescence display apparatus is superior in a viewing angle characteristic.
A driving method of the flat-panel display apparatus, especially the organic electro-luminescence display apparatus is mainly classified into two. That is, one is a simple matrix type driving method and the other is an active matrix type driving method. The simple matrix type driving method is suitable for a small-size display apparatus such as a mobile terminal because the structure is simple. However, the method has a problem in a response speed. Therefore, it is not suitable for a large-size display such as a television screen. Thus, the active matrix type driving method is used for a television and a personal computer. As a technique applied to the active matrix type driving method, a TFT (Thin Film Transistor) active matrix method is widely known, in which TFT is used as a pixel. For example, a TFT active matrix method is disclosed in Japanese Laid Open Patent Application (JP-P2003-195812A). The TFT active matrix method is further classified into two. One is a voltage drive type, and the other is a current drive type.
FIG. 1 is a block diagram showing the circuit configuration of a conventional organic electro-luminescence display apparatus 100. As shown in FIG. 1, the display apparatus 100 includes a data line driving circuit 101, a scanning line driving circuit 102, a control circuit 103, and a display panel 104. The display panel 104 has a plurality of data lines 111 arranged in a column direction, i.e., a vertical direction. Each data line 111 is connected with the data line driving circuit 101. Similarly, the display panel 104 has a plurality of scanning lines 121 arranged in a row direction. Each scanning line 121 is connected with the scanning line driving circuit 102. In addition, the display panel 104 has a pixel 105 at each of intersections of the plurality of data lines 111 and the plurality of scanning lines 121.
The data line driving circuit 101 and the scanning line driving circuit 102 are connected with the control circuit 103. The data line driving circuit 101 supplies a voltage or current to each of the plurality of data lines 111 in response to a pixel control signal outputted from the control circuit 103. The scanning line driving circuit 102 supplies a voltage or current to each of the plurality of scanning lines 121 as well as the data line driving circuit 101 in response to the pixel control signal outputted from the control circuit 103.
The control circuit 103 controls the data line driving circuit 101 and the scanning line driving circuit 102. The control circuit 103 receives display data to be displayed on the display panel 104 and a control signal corresponding to the display data, and outputs the pixel control signal based on the display data and the control signal. The pixel control signal is to control the data line driving circuit 101 and the scanning line driving circuit 102. The display panel displays the display data as a display image by driving a light-emitting element of each pixel 105 based on the outputs of the data line driving circuit 101 and the scanning line driving circuit 102.
The display apparatus 100 shown in FIG. 1 is driven based on a sequential line driving and scanning method. The scanning line driving circuit 102 drives the plurality of scanning lines 121 in a predetermined order in response to a scan sync signal. The data line driving circuit 101 drives the plurality of data lines 111 in relation to the scanning line 121 selectively driven by the scanning line driving circuit 102 so that the pixel 105 displays the display data. The data line driving circuit 101 drives each data line 111 by dividing a period for displaying the display data (to be referred to as a data line drive period) into two periods, one being a first period to referred to as a precharge period and a second period to be referred to as an current drive period.
FIG. 2 is a circuit diagram of the pixel 105 of the display apparatus 100 in the active matrix type driving method. As shown in FIG. 2, the pixel 105 includes an electro-luminescent element 130 as a light-emitting element, a drive TFT 131, a switch 132, and a capacitor 135. The electro-luminescent element 130 emits light in accordance with an EL (Electro Luminescence) phenomenon. The drive TFT 131 is connected between the electro-luminescent element 130 and a ground potential GND. The source of the drive TFT 131 is connected with the ground potential GND. The switch 132 is provided for each pixel 105 which is arranged in each of the intersections of the data lines 111 and the scanning lines 121. The switch 132 is connected with the gate of the drive TFT 131 through a node 133. The capacitor 135 is a capacitive element. As shown in FIG. 2, the capacitor 135 is connected between the node 133 and the ground potential GND.
FIG. 3 is a block diagram showing the circuit configuration of the data line driving circuit 101. As shown in FIG. 3, the data line driving circuit 101 includes a shift register circuit 112, a data register circuit 113, a data latch circuit 114, a D/A conversion circuit 115, an input buffer circuit 116, a timing control circuit 117, and a reference current source 118. The data register circuit 113 is a memory circuit to store the display data. The data register circuit 113 stores the above-mentioned display data in synchronism with a signal outputted from the shift register circuit 112. The data latch circuit 114 reads out the display data stored in the data register circuit 113 in synchronism with a latch signal from the timing control circuit 117, and outputs the read data to the D/A conversion circuit 1. The D/A conversion circuit 115 generates a current to be outputted onto the data line based on the data from the data latch circuit 114.
The input buffer circuit 116 carries out bit inversion to the display data based on an inversion control signal in synchronism with a clock signal CLK and outputs the inverted result to the data register circuit 113. The timing control circuit 117 controls operation timings of the data latch circuit 114, the D/A conversion circuit 115, and the reference current source 118 in response to a horizontal sync signal STB in synchronism with the clock signal CLK. The reference current source 118 provides a reference current to the D/A conversion circuit 115. Therefore, in the data line driving circuit 101 shown in FIG. 3, the serial display data is converted into parallel display data through the operations of the shift register circuit 112 and the data register circuit 113. The parallel display data is outputted to the data latch circuit 114. The data latch circuit 114 latches the parallel display data in synchronism with the scanning of the scanning lines. The D/A conversion circuit 115 reads out the parallel display data latched by the data latch circuit 114 for each scanning line, and outputs the display data sequentially during a horizontal drive period.
FIG. 4 is a circuit diagram showing the circuit configuration of the D/A conversion circuit 115. As shown in FIG. 4, the D/A conversion circuit 115 includes a converter circuit 151 and a precharge circuit 152 for every one or more data lines. The converter circuit 151 carries out D/A conversion of a plurality of reference currents weighted in a binary manner by using the display data to generate gradation currents for the display data. The precharge circuit 152 includes a quasi-addition circuit 153, a voltage driver 154, and switches 155, 156, and 157. The precharge circuit 152 generates a gradation voltage adaptive for the input impedance characteristic of the pixel 105 based on the gradation current from the converter circuit 151 by the quasi-addition circuit 153 and the voltage driver 154 which have the same impedance characteristic as the input impedance characteristic of the pixel 105 shown in FIG. 2. In addition, the precharge circuit 152 outputs a gradation voltage and gradation current to carry out the voltage drive and current drive of the data line in the order of the precharge period and the current drive period in one horizontal drive period through switching of the switches 155, 156, and 157.
In the data line driving circuit 101, the data line drive period for the drive of the data line is divided into the two periods of the precharge period and the current drive period. In the precharge period, the data line driving circuit 101 drives the data line 111 by a voltage drive circuit with a high drive ability (Hereinafter, this drive is referred as a voltage drive). In the current drive period, the data line driving circuit 101 drives the data line 111 by a constant current source circuit in a current with a constant current value (Hereinafter, this drive is referred as a current drive). The data line driving circuit 101 outputs the gradation voltage in the precharge period to drive the data line 111 in the voltage drive. The capacitor 135 for each pixel 105 is charged up to a predetermined voltage in a short time with the outputted gradation voltage. In addition, the pixel 105 is driven in high accuracy by the gradation current outputted from the data line driving circuit 101 in the current drive period so as to achieve display with high accuracy.
In the conventional display apparatus 100, the display data is converted so as to be adaptive for a specific gamma characteristic by the driving circuit. For instance, when the display data from a CPU is of 6 bits, the display data is converted to have increased bits for producing the display data adaptive to the gamma characteristic. The conversion of the display data is carried out by the control circuit 103. In the above Japanese Laid Open Patent Application (JP-P2003-195812A), the control circuit 103 converts the display data to have 10 bits or more in accordance with a conversion table, and supplies the converted display data to the data line driving circuit 101. At this time, the data line driving circuit 101 is required for the D/A conversion circuit 115 to have the resolution of 10 bits or more to drive the data line based on the converted display data. The converter circuit 151 of the D/A conversion circuit 115 is provided with transistors which have a same channel length L but different channel widths W of 2n. Otherwise, the D/A conversion circuit 115 may be provided with transistors which have the same channel length L and the same channel width W and which are controlled in accordance with different reference currents of 2n. If the display data is of 10 bits, the circuit scale has to be large because the converter circuit 151 is provided with at least ten transistors. Especially, in the former configuration, since the channel width W is dependent on 2n, the chip area is enlarged very much. In addition, power consumption becomes large in an interface between the control circuit 103 and the data line driving circuit 101 because the number of bits is increased. Moreover, an output capacitance becomes large because the D/A conversion circuit 115 in the data line driving circuit 101 is provided with the plurality of transistors. Here, a current I, a drive voltage V, a capacitance C, and a driving time T satisfy the following relation:I=CV/T The time T is determined from the number of scanning lines and a frame frequency. Therefore, the current value is increased as the capacity increases. As a result, it is difficult to drive the data line in a low current level. A driving circuit with a small chip area is required for a display apparatus. In addition, a driving circuit in low power consumption is required for a display apparatus.
Moreover, a transparent substrate (for instance, a glass substrate) is used for the display panel 104 in the conventional display apparatus 100. When the display panel 104 is manufactured by using the glass substrate, a deviation in characteristics of the transistors formed on the glass substrate is ten times or more larger than that in characteristic of the transistors formed on a silicon substrate. Therefore, if the data line driving circuit is formed on the glass substrate, ununiform display tends to be generated easily. Thus, the data line driving circuit is preferably formed on the silicon substrate. Forming the data line driving circuit 101 on the silicon substrate, it is difficult that the quasi-addition circuit 153 included in the data line driving circuit 101 has the same characteristic as the pixel 105 formed on the glass substrate, resulting in decrease in the reliability of the circuit. Thus, a driving circuit for the display apparatus with high reliability is required.
Furthermore, when a switching is carried out from the voltage drive to the current drive, glitch is generated sometimes in the conventional display apparatus 100. The glitch causes lowering image quality, especially in a low brightness (low current region) because a voltage is drifted from a desired voltage, even if the voltage is precharged to a desired voltage at high speed by the voltage driver. Therefore, a display apparatus is demanded in which the image quality and reliability are improved, while restraining the generation of the glitch.
In conjunction with the above description, an EL display apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2003-223140A). In this conventional example, the EL display apparatus includes an EL element. A drive circuit drives the EL element in current in accordance with a PAM method in correspondence to a gradation level of display data. A precharge circuit applies a precharge voltage corresponding to the gradation level before the drive circuit supplies the current to the EL element.
Also, an EL storage display apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 2-148687). In this conventional example, the EL storage display apparatus includes a brightness control circuit, an EL element, a plurality of memory elements provided for the EL element, and a current source connected with the EL element. A plurality of current control elements are respectively provided for the memory elements, and control a current supplied from the current source to the EL element based on signals stored in the memory elements. The signal indicating a brightness requested from the El element is supplied to the memory element.